25
8024A–AVR–04/08
ATmega8HVA/16HVA
9.1.5
Coulomb Counter ADC Clock - clk
CCADC
The Coulomb Counter ADC is provided with a dedicated clock domain. This allows operating the
Coulomb Counter ADC in low power modes like Power-save for continuous current
measurements.
9.1.6
Watchdog Timer and Battery Protection Clock
The Watchdog Timer and Battery Protection are provided with a dedicated clock domain. This
allows operation in all modes except Power-off. It also allows very low power operation by utiliz-
ing an Ultra Low Power RC Oscillator dedicated to this purpose.
9.2
Clock Sources
The following section describe the clock sources available in the device. The clocks are input to
the AVR clock generator, and routed to the appropriate modules.
9.3
Calibrated Fast RC Oscillator
The calibrated Fast RC Oscillator by default provides a 8.0 MHz clock to the system clock pres-
caler. The frequency is nominal value at 70
°C. This clock will operate with no external
components. With an accurate time reference and by using runtime calibration, this oscillator
can be calibrated to an accuracy of +/- 1. % over the entire temperature range. During reset,
hardware loads the calibration byte into the FOSCCAL Register and thereby automatically cali-
brates the Fast RC Oscillator. At 70
°C, this calibration gives a frequency of 8 MHz ± 4%. The
oscillator can be calibrated to any frequency in the range 7.3- 8.1 MHz by changing the FOSC-
CAL register. For more information on the pre-programmed calibration value, see the section
”Reading the Signature Row from Software” on page 144. Note that the frequency of the system
Start-up time of the chip is referred to as a number of Prescaled Fast RC Oscillator cycles (CK)
and a number of ULP oscillator cycles. The start-up time is selected by SUT fuses as defined in
Notes:
1. The device is shipped with this option selected.
2. The actual value of the added, selectable 4- 512 ms delay depends on the actual frequency of
Table 9-1.
Start-up times according to SUT fuse selection.
SUT3..0
Start-up Time from
Power-save
Additional Delay from Reset, Typical Values(2)
000
6 CK
14 CK + 4 ms
001
6 CK
14 CK + 8 ms
010
6 CK
14 CK + 16 ms
011
6 CK
14 CK + 32 ms
100
6 CK
14 CK + 64 ms
101
6 CK
14 CK + 128 ms
110
6 CK
14 CK + 256 ms
6 CK
14 CK + 512 ms
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